1. Field of the Invention
The present invention relates to a method for implementing an interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as a corresponding sender side or receiver side, for connection to the FPGA. Further, the invention relates to an FPGA control system with at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA.
2. Description of the Background Art
Shorter cycle times of control circuit models are increasingly required in high-end applications. For this reason, such control circuit models based on control algorithms are often implemented in FPGA control systems in field programmable gate arrays (FPGAs), as a result of which very rapid control circuits with sampling rates of 100 ns to 5 μs can be implemented. The control circuit models can be designed as modular. These modular FPGA circuits or model FPGA circuits in prototyping systems usually do not have suitable I/O wiring, in order to be able to operate directly the necessary sensors and/or actuators.
Thus, an adaptation for the sensors and/or actuators is necessary, which occurs via I/O modules. The I/O modules can produce, for example, a connection to the model hardware via a connector system, i.e., the FPGA, whereby direct connectors for attaching the I/O modules or cable connectors can be used.
It is problematic in such a modular system to connect any I/O modules with a low latency and high bandwidth to the model FPGA.
In order to solve this problem, defining a suitable interface with a suitable protocol for each specific I/O module is known from the state of the art. As a result, a low latency at the highest bandwidth possible can be achieved. Nevertheless, each defined interface must be set up specifically both on the side of the FPGA application and for the particular I/O module, which is associated with a high cost.
Alternatively, implementing modular buses, which usually have a fixed maximum attainable bandwidth and latency, is known from the state of the art. Different modular systems are known in which the connection occurs via address data buses. In this regard, a distinction is made in principle between parallel buses, e.g., PHS bus or ISA bus, and serial buses, e.g., PCI Express.
In the case of parallel buses, the bandwidth is usually determined by the number of available data lines. In a bus with N data lines, the latency is identical during the transmission of 1 or N bits. The maximum achievable bandwidth and latency are identical for all I/O modules.
In the case of serial buses for modular systems, a protocol is used in which the actual payloads are embedded. These known protocols have a minimum protocol overhead, which independently is identical for the transmission of, for example, 1 bit or 32 bits, when a minimum payload amount is established by the protocol. For example, only n*bytes (8 bits) or n*32 bits can always be transmitted. If only one payload bit is to be transmitted, nonetheless, the complete minimum payload volume must be transmitted. The bandwidth and the latency deteriorate because of the protocol overhead and the minimum payload volume in comparison with a specific implementation of the interface.
A constant data rate may also be necessary depending on the employed FPGA models. Deviations from the constant date rate are called jitter.
The above statements each refer to a sender and receiver side, i.e., a unidirectional interface. Implementation of the FPGA application and of the I/O module as a sender or receiver side is thereby interchangeable. Moreover, the interface can also be designed as a bidirectional interface.